Workshop On Design Of Low Power VLSI Circuits Using EDA Tool

The Department of Electronics and Communication Engineering, associated with IETE Palakkad center, organized a two day workshop on “Design of Low Power VLSI Circuits using EDA tool” on 26th and 27th of February 2018. Mr. Kavin Kumar M. and Mr. Gavaskar, Assistant professor of Kongu Engineering College, Erode, were the resource persons. On the first day, a brief introduction was given on Tanner EDA tool for designing low power VLSI circuits. The second day session concentrated on delay and power analysis of CMOS logic circuits. The students received hands-on training on various CMOS logic designs with the help of this tool.